Final Project

Due in your discussion section the week of April 8th. You must show the TA a high-level ASM chart for your project and a detailed block diagram for your design.

Due in your discussion section the week of April 15th. You must show the TA an ASM chart for your FSM control and Verilog code for your design though it does not need to be completely functional.

You must be able to demo a fully functioning CPU or MTG. This demo includes correct functionality in both the user mode and the run mode. CPU: User Mode (35 pts): In the user mode, the CPU should allow the user to input instructions using the switches and then pressing the instruction ready (or sample) button. Run Mode (35 pts): In the run mode, the CPU should execute predefined instructions stored in the ROM module and output the final result of the application to the LEDs. You must be able to show your application instructions and explain what the application does. Try to make the application do something interesting (eg. Fibonacci sequence or Hailstone sequence). MTG: User Mode (25 pts): In the user should be able to play notes A-G using three different push buttons. The notes should continue to output from the speaker for as long as the buttons are held Run Mode (45 pts): In the run mode, the MTG should play the Habanera song as given on Canvas. Pick a tempo that is not too fast, but not too slow. You should be able to show how you constructed you ROM that contains the song. Please note the partial credit that can be received for the project demo.

Top Level Block Diagram (10 pts) Clearly label all blocks, wires, and I/Os. ASM Chart for each controller (10 pts) Clearly label all states, transitions, and I/Os. Report Summary: 3 - 5 pages (20 pts) Format in a professional and presentable manner. Clearly state all assumptions, optimizations, and design decisions made for the project. Describe the testing strategy used to verify the project's functionality. Also, tell us any lessons learned from implementing the project. Verilog & Testbench files (25 pts) Simulation Plots showing adequate functionality of the circuit (25 pts)