Lab #5 - Synchronous Sequential Circuits

Demonstrate a fully-functioning finite state machine (FSM) that controls your universal shift register (USR), as described in homework 5. Checkoff will be performed by first pressing the reset button, then performing different load/shift sequences using the three other buttons/switches. The output of the USR should be seen on 4 LEDs.

Include the circuit's RTL schematic generated from Quartus (screenshot or pdf format). Report on the area and delay of your circuit.

Must include connection to USR

Design the test to be self-checking and thorough enough to convince yourself and your TA that the FSM and USR are working properly together.

Display enough information to validate your test-bench and show that your design is functioning properly (again, with the FSM and USR connect) . Include console output.