ECE 6750-001 Spring 2018 Syn & Ver Asyn VLSI Sys

ECE/CS 5750/6750 
Asynchronous Circuit Design 
Spring 2018

Course description

In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to environmental and processing variations, provide component modularity, and lower system power requirements. There is, however, a widely held belief that asynchronous design is difficult and leads to inefficient and unreliable designs. The goal of this course is to dispel this belief by introducing a systematic approach to the design of asynchronous VLSI systems from a high-level specification to an efficient and reliable circuit implementation. This course will include both hands-on experience with existing CAD tools as well as learn the algorithms within them. Topics will include: specification, synthesis, optimization with timing information, performance analysis, and verification.

Instructor

Instructor: Chris Myers

Prerequisites

Students should have a familiarity with computer programming (CS 2010-2020) and digital logic design (ECE/CS 3700).

Textbooks

Asynchronous Circuit Design by Chris J. Myers published by Wiley.

Grading Policy

Project

A major emphasis of this course will be a final individual project. Students will choose one topic from the course, find research papers on that topic, and implement a computer aided design (CAD) tool. Each student must present the project both in a written report and an oral presentation. The written project report should be four pages in the IEEE two column format described here.

ECE/CS 6750

Students taking ECE/CS 6750 will be expected to solve extra homework problems and complete a more extensive project.

Meeting Times

College guidelines are linked here.