Course Syllabus

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CS/ECE 5710/6710
Digital VLSI Design
Fall 2015

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Instructor:	Erik Brunvand, elb 'at' cs 'dot' utah 'dot' edu, MEB 3142
Office Hours:	After class and by appointment
TAs	Daniel Khoury and Sarvani Kunapareddy
TA Office Hours	UPDATE AS OF 10/19/2015 Mondays: 10:00 AM to 2:00 PM (Sarvani) Tuesdays and Thursdays: 2:00 PM to 5:00 PM (Sarvani, Daniel) Wednesdays: 10:00 AM to 2:00 PM (Daniel) Fridays: No office hours Here's an on-line queue that you can use during TA office hours to request TA help.  http://nine.eng.utah.edu/schools/uofu/elb/CS6710/login
Class:	T - Th 5:15-6:35 in WEB 2230
Contact	Send email to teach-6710@list.eng.utah.edu

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Logistics

• Prerequsites: Digital Logic (CS/ECE 3700 or equivalent) is required. Computer organization (CS/ECE 3810 or equivalent) will be extremely helpful. 
  
  
• Textbooks: 
• Principles of CMOS VLSI Design: A Circuit and Systems Perspective (4th Edition), By Neil Weste, David Harris, Published by Addison-Wesley, c2010, ISBN 978-0321547743. Note that there are some Errata (mistakes) that are listed here.
• We'll also use Digital VLSI Chip Design with Cadence and Synopsys CAD Tools by Erik Brunvand as a lab manual. Published by Addison-Wesley, c2010, ISBN 978-0321547996. This book is available at a special price in a bundle with the CMOS VLSI Design textbook. That bundled version should be what is available in our University of Utah bookstore
  
• The lab manual was written for the v5 Cadence tools. We're now using the v6 tools. There's a v5-to-v6 transition guide for the Digital VLSI Chip Design book available here. 
• Because there have been some issues with the bookstore having enough copies of the CAD book, I'll link the first few chapters here. Please do not let these chapters "escape" to the web! Also, you'll have to access these from a machine in the .utah.edu domain. 
• Chapter1
• Chapter2
• Chapter3
• Chapter4
• Chapter5
• Chapter6
• Chapter7

• Academic Misconduct (Cheating): The School of Computing Academic Misconduct Policy is in effect for this course. Every student should read the policy here. You will be asked to sign on the first assignment that you read and understood the policy. Note that the default sanction for any academic misconduct offense is a failing grade for the course. Note also that it's easy to avoid - just don't cheat! A discussion of this issue as it relates to this class can be found here.
  • If you have NOT already filed one of these forms with the SoC office, please print this, sign it, and submit it to the TAs in class. All students who have not already filed this form MUST sign and return the form. Thanks. You can download the form here
    
    
• College guidelines for adding, dropping, and other administrative issues can be found here. 
  
  
• The University of Utah provides reasonable accommodation to the known disabilities of employees and students. If you need special accommodations, please contact University Disability Services and let the instructor know at the beginning of the semester.
  
  

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Course Information

This is an introductory course in VLSI where you will go from the low level physical transistor and mask design of your own cell library, all the way to the design, implementation, and fabrication of a significant digital integrated circuit.

Many aspects of Digital VLSI design will be introduced in order to take this significant and enjoyable design journey. However, note that this is not a course in digital system design or computer architecture. You will already need to know boolean logic and how to design and implement combinational and sequential digital circuits (such as adders and other datapath logic, and finite state machines). The project will also require some knowledge of computer architecture for you to complete a moderately large digital design.

Topics that will be covered in lectures include:

Basic transistor theory
CMOS processing
Mask layout and design rules
VLSI CAD tools
Circuit simulation and characterization
Custom datapath circuit design
Standard cell design and use
Library-based circuit synthesis
Full chip assembly

The class will require extensive use of Computer Aided Design (CAD) tools (sometimes these are classified as Electronic Design Automation (EDA) tools). All of the CAD tools required will be available in the CADE lab. Students must have an account that will allow them to use the CADE machines. These tools do not run on Windows. Therefore some familiarity with Linux and the X window system is required for this course.

The tools will be discussed in class and the TAs know how to use the tools and will hold office hours in the CADE lab to help. However, there is no specific lab class that you are required to attend. You can perform the labs and your project at your own convenience, either in the CADE lab at the University, or across the network. Remember that nothing can replace taking the time to read the CAD tool documentation, or follow along in the CAD book..

Integrated circuit design is mastered only through experience, so this is a hands-on course with lots of labs and project time required. The homework, as well as lectures, will be closely tied to the term project, the design of a simple standard cell library and then the use of that library to design a project. The initial design of cells for the project will be done individually. You must complete the design of these cells on time. You are encouraged to interact with others, but until you are asked to form teams, the work on your cell designs, simulations, etc., must be your own.

The final library and project will be done in teams of 3-4 students. The project must be completed, and you must submit a final report in the format specified.

Fabrication of your final project is possible thanks to funding provided through the MOSIS service. Little is more rewarding that creating a functional integrated circuit. Little is more disappointing than spending time on a design only to have in be non-functional. Therefore, careful design practices must be followed if you are to fabricate your chip including sufficient Design-For-Test, validation of your design, and a quality design review. If you do fabricate the chip, you will be required to take ECE/CS 6712 in Spring 2016 (1cr) to test and report on the results. 6712 is a fun class and a reward to those who make the effort to fabricate their designs.

 

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Lecture Schedule
(This is an initial schedule, things may change a little during the semester)
(Slides and readings will be updated as the semester progresses) 

 

Week	Lecture Topics	Lecture Slides	Reading
8/25, 8/27	Introduction and switch-level circuits	Introduction Slides: IntroX2.pdf Slides on switch level circuits| Additional slides from David Harris on switch level circuits Here are some slides on basic  electronics from a long-ago  version of CS3700.	Chapter 1, Sections 1.1-1.4
9/1, 9/3	More transistor switch-level circuits Intro to layout and design rules Simple Verilog for testbenches	Slides on CMOS layout Slides on Verilog testbenches Pictures of chips	Section 1.4 looking forward  to Chapters 9 and 10
9/8, 9/10	More layout issues Line-of-diffusion and Euler paths	More about CMOS layout Slides on VLSI sketchbooks  An old handout on routing with 3 layers of metal	Sections 1.5.2-1.5.5 and Section 3.3
9/15, 9/17	MOS transistor theory and behavior	Slides on MOS transistor theory	Chapter 2 and some of Chapters 5 and 6 on power  and interconnect
9/22, 9/24	CMOS processing and fabrication	Slides on CMOS processing and  fabrication Video from Global Foundries	Section 1.5 and Chapter 3
9/29, 10/1	Logical effort transistor sizing and analysis Review of CAD3 register layouts	Slides on Logical Effort transistor sizing Chapter 1 from Sutherland and Harris: Logical Effort	Chapter 4, especially sections  4.4 and 4.5
10/6, 10/8	CAD5 introduction Verilog for synthesis and synthesis overview	Slides about CAD5 - ELC and Abstract generation Slides on Project Ideas Slides on Verilog used for synthesis	CAD Book Chapters 8 & 10 Weste/Harris Appendix A
10/13, 10/15	No class - Fall Break!
10/20, 10/22	Synopsis synthesis overview Cadence EDI place and route	Daniel will lecture on Synopsys Design Compiler on Tuesday Sarvani will lecture on Cadence EDI on Thursday These are both ESSENTIAL tools for your project don't miss these lectures!!!! Slides on Synopsys Design Compiler (synthesis) and Cadence Encounter Digital Implementation (place and route)	CAD Book Chapters 9 & 11 Weste/Harris Appendix A
10/27, 10/29	Mini-MIPS example - small processor VGA circuits	Slides on the mini-MIPS processor from the Weste/Harris textbook Slides on VGA circuits and interfaces  "Mini Project" from 2005 related to VGA interfaces.  Handout about the MemcellsF09 memory cells	Weste/Harris Sections 1.7 & A.12, & chapter 11 CAD book chapters 11 & 12
11/3, 11/5	NO LECTURES - Sign up for group  project proposal meetings during class time
11/10, 11/12	More group meetings, no general lecture on Tuesday MID-TERM EXAM on Thursday 11/12	Here's a sample midterm to give you an idea of the types of things that might be asked on the midterm. Of course this year's midterm might cover different material - anything from the homework/CAD assignments is fair game!
11/17, 11/19	Chip assembly using CCAR Pads and pad rings	Slides on chip assembly using CCAR Slides on pads and pad rings Slides inverter footprints
11/24	No lecture on Tuesday - I'll be in the CADE lab helping with issues/questions during  class time Thanksgiving Holiday on 11/26
12/1, 12/3	NO LECTURES - sign up for group  design reviews
12/8, 12/10	Student project presentations in class	10-minute lightening talks on your projects. You must give me your slides in advance so I can put them all in one computer!
12/16	Final reports due
1/15/2016	Final GDS files due for fabrication!!

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Assignments and Labs are found at the bottom of this page...  

These chapters in the Weste/Harris textbook are directly related to the labs. These sections in the textbook will be extremely helpful as you work on these lab assignments. 

CAD1 - Schematics and Verilog: Chapter 1, and Appendix A
CAD2 - layout / DRC/ LVS: Chapter 3 (layout) and Chapter 8 (simulation)
CAD3 - Flip Flop Design: Chapter 3 (layout) and Chapter 10 (sequential circuit design)
CAD4 - DC analysis and Spectre: Chapter 2 (MOS device theory), Chapter 4 (delay),  and Chapter 8 (simulation) 
CAD5 - Five-cell Library: Chapter 9 (combinational circuit design)
CAD6 - Extending your Library: Chapter 9 (combinational circuit design) and Chapter 10 (sequential circuit design)
CAD7 - Adding drive strengths: Chapter 4 (delay)
Proposal - Project Proposal: Chapter 11 (datapath subsystems), Chapter 12 (array subsystems), and Chapter 14 (design methods)

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Grading Policy

Refer to the College of Engineering Guidelines for more detail on appeals, disabilities, adding, and withdrawing from courses.

Grading will be based on participation. Note that I expect you to submit homework and labs on time. There is generally no possibility of turning in late work - in a large class and with labs happing on a regular schedule late work quickly becomes unmanageable. The due dates will be known long in advance so that you can plan for this. If there are exceptional circumstances, let me know. If there are exceptional circumstances that are class-wide, adjustments to the due dates might be given for the whole class. 

Expected participation includes:

• Homework: Written homework will take the form of problem sets, project proposals, and other written work.
• Labs: Labs involve mask-layout design of cells that will be used in your semester project. We will use CAD tools from Cadence and Synopsys runing on linux in the CADE lab.
•  Design Review: A short presentation on your project given to the class.
•  Mid-term Exam: There will be one exam given sometime in the middle of the semester.
• Class Project: The class project will require the design of a small digital standard cell library that will then be used as a target library for a moderate sized chip design. Class members will join design teams for the implementation of the design. More details on the format of the final report will be available later in the semester.
• Graduate Students: Those taking the graduate level course will have additional requirements that include a more rigorous project or design flow and the review of two papers relating to VLSI from journals or conferences in the area. These could be related to the project being implemented. For graduate students the labs will be 35%, and the paper reviews will be 5%. 
  
  
• Percentages for grades are as follows:
  • Labs (cell designs) & Homework: 40%
  • Design Review: 5%
  • Mid-term Exam: 15%
  • Project (design and report) 40%

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Tool Information (Cadence, Synopsys, Verilog, etc. )

• Verilog Information
  • Here's a site with some Verilog tutorials that seem quite nice
  • Single-page reference sheet on Verilog syntax. 
  • A Verilog Quick Reference guide 
  • Another Verilog Quick Reference guide (perhaps the same one reformatted...) 
  • A Verilog 2001 reference guide
  • Yet another Verilog guide. This one is an introduction to Verilog from Daniel C. Hyde at Bucknell University. This guide is targeted at simulation
• A set of documents from Synopsys that describe good Verilog coding style for synthesis. They are all in linked PDF. Open the Table of Contents and you should be able click on the chapters in that file to open up the chapters.
  Note that these files are only accessible to CS/EE 5710/6710 students     
  • Table of contents      
  • Chapter 1  : Coding Styles for if Statements and case Statements
  • Chapter 2  : Coding if and case Statements for Late Arriving Signals
  • Chapter 3  : Coding Styles for Logic Building Blocks
  • Chapter 4  : High Performance Coding Techniques
  • Chapter 5 : General Coding Style Guidelines
• A reference manual from Synopsys describing the Verilog synthesis engine.
  Note that these files are only accessible to CS/EE 5710/6710 students     
  • Table of contents      
  • Chapter 1 : Introducing the HDL Compiler for Verilog    
  • Chapter 2 : Description Styles   
  • Chapter 3 : Structural Descriptions     
  • Chapter 4 : Expressions
  • Chapter 5 : Functional Descriptions     
  • Chapter 6  : Register, Multibit, Multiplexer, and Three-State Inference   
  • Chapter 7  : Resource Sharing
  • Chapter 8  : Writing Circuit Descriptions
  • Chapter 9  : HDL Compiler Directives   
  • Chapter 10 : Design Compiler Interface     
  • Appendix A : Examples
  • Appendix B : Verilog Syntax

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Helpful Information

• Other books you might find useful (there are lots and lots of good VLSI books out there - these are just a few!):
• Logic Effort - designing fast CMOS Circuits, I. Sutherland, B. Sproull, and D. Harris. Academic Press, 1999
• Analysis and Design of Digital Integrated Circuits (3rd ed), David Hodges. McGraw Hill, 2004.
• The Design and Analysis of VLSI Circuits, Glasser and Doberpuhl. Addison-Wesley, 1985 (still surprisingly useful)
• CMOS Digital Integrated Circuits Analysis & Design 4th Edition, Sung-Mo (Steve) Kang, Yusuf Leblebici, Chul Woo Kim, 2014
  
  
• Off-chip Memory Chips - these are 32kx8 chips (256k bits) that you can use as examples for the types of off-chip memories you could use in your projects. I have some of each of these specific chips that you can use if you fab your chip and want to build an example system. You can, of course, also search hardware vendors for other memory chips that have different specs if you like. Remember that our process (ON Semi, C5N) has a 5v power supply. That may limit the types of chips you can use easily. 
• 242376CYPRESS.pdf - This is a 32k static RAM (SRAM) - I have the -35 versions (35ns read access time). 
• 266079CYP.pdf - This is an EPROM that you can program using the EPROM programmer in the digital lab. I have the 55ns access time version. (32kx8)
• 394986.pdf - This is a one-time-programmable 32kx8 ROM. You can burn this in our prom burner, but once it's burned, it can't be changed. I have some of the 45ns access time versions. Its slightly faster, and in a slightly smaller package than the EPROM above. 

• VGA Information
  • Here's a link to a page with lots of VGA timing info. Note that this is "official timing" information, and most VGA displays are quite forgiving if you are consistent with your own timing.
  • This page from the XESS company has some examples of VGA controllers targeted at their Xilinx-based boards. So, memory details would have to be finessed for custom chips, but the basics might be interesting. The appnote for the simple controller for the ancient XS-40 board is a good basic design, although it's in VHDL in the appnote...
• The VGA mini-project from 2005 which has lots of details on how to get a VGA controller working. Check out the text message option for details on using the charROM to make characters on the screen.
  Note that some of the details from 2005 aren't relevant any more, like the stuff about Silicon Ensemble. We now use EDI. But,the specs on VGA are still good.
• Here's a link to a site with information about interfacing to a PS/2 keyboard and mouse. It describes the timing interface and the communication protocol that keyboards and mice use to send data through that link. Note that PS/2 keyboards, for example, don't send ASCII. They send "make codes" and "break codes" on key press and key release that encode which physical key has been pressed. You need to map those keys to the letters using those codes if you want ascii.
• Chapter one from Sutherland, Sproull, and Harris' book on Logic Effort is here in PDF.
• A document by Eric Marsman from University of Michigan that describes a layout and floorplanning approach in a three metal process. This is a nice basic guide to planning interconnect issues. It's in PDF.
• A guide to basic electronics including MOS transistors: Appendix B from Contemporary Logic Design by Randy Katz. You don't need to know the sections on bipolar or diode logic. The MOS section is the most important.
• The SCN3M_SUBM SCMOS design rules from MOSIS, translated to microns, in PDF format, and in Word format.
  • The SCMOS design flow page at MOSIS
  • The official SCMOS rules from MOSIS
  • MOSIS (MOS Implementation Service) home page
• A link to Reid Harrison's CS/EE 5720/6720 Analog VLSI class. They are also using the NCSU CDK and the SCMOS rules so you can find more information here including tutorials on analog simulation of designs built with the NCSU CDK, and a layout tutorial. (Note that this is an older version of this course that Reid taught when he was faculty here at the U. He's now at Intan Technologies in Santa Monica, a company he founded)
• Paper formatting information:
  • LaTeX style files for producing IEEE-formatted two-column papers: A .cls style file with formatting information, a .bst bibliography style file, and a sample .tex file that demonstrates how it all should be used.
  • A Microsoft Word example file that shows how to get an IEEE format in MS Word.
• A data sheet on the HM6264 8kX8 SRAM from the DSL lab kits. This is a good example of a generic SRAM that shows read and write protocols.
• Documentation from Tanner Research about their digital pads in PDF. We'll be using these pads for our chip designs.
• A page from Americn Microsemiconductor that has lots of tutorials on various semiconductor topics.
• Here's a paper that I wrote a few years ago that describes a simple stack based architecture similar to the transputer that might make a great project. Even if you don't use this exact architecture, stack-based machine make nice simple processor architectures for those wanting to do a processor project. You definitely don't have to do this as a self-timed processor! It's a perfectly good synchronous stack machine too.
• Here are a couple papers from the Journal of Solid State Circuits about latches and flip flops. These are just a couple examples, there are lots of papers about this! These papers analyze different latch and flip flop circuits for speed and power performance.    
  • Comparative Analysis of Master Slave Latches and Flip-Flops for High-Performance and Low-Power Systems by Vladimir Stojanovic and Vojin G. Oklobdzija    
  • New single-Clock CMOS LAtches and Flipflops with Improved Speed and Power Savings by Jiren Yuan and Christer Svensson
• Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies by Nguyen Minh Duc and Takayasu Sakurai. This paper makes a case that a small (11 or 20 cells) library can perform almost as well as a 400 cell library when used with Synopsys design compiler and standard benchmarks.

 

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