Course Modules

General References/Resources

General References/Resources
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General References/Resources 4205951  
  • Attachment
    Verilog Crash Course Verilog Crash Course
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    Online Resources Online Resources
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Discussion Sections

Discussion Sections
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Discussion Sections 4205952  
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    Discussion Section 1 (Week 6): CMOS, Overflow, Signed Multiplication Discussion Section 1 (Week 6): CMOS, Overflow, Signed Multiplication
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  • Page
    Discussion Section 2 (Week 7): Adder Design, Decoders, Comparator Design Discussion Section 2 (Week 7): Adder Design, Decoders, Comparator Design
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Module 0: Introduction

Module 0: Introduction
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Module 0: Introduction 4205953  
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    Module 0: Overview Module 0: Overview
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Module 1: Introduction To Digital Systems (Ch. 2 + App B)

Module 1: Introduction To Digital Systems (Ch. 2 + App B)
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Module 1: Introduction To Digital Systems (Ch. 2 + App B) 4205954  
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    Module 1: Overview Module 1: Overview
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  • Page
    Week 1: Digital Circuit Design Application, Digital Abstraction, Boolean Functions Week 1: Digital Circuit Design Application, Digital Abstraction, Boolean Functions
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    Week 2: Boolean Functions, Universal Logic, Circuit Synthesis, K-Maps Week 2: Boolean Functions, Universal Logic, Circuit Synthesis, K-Maps
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    Week 3: Universal Logic, Karnaugh Map, Binary Decision Diagram, Logic Gates Implementation Week 3: Universal Logic, Karnaugh Map, Binary Decision Diagram, Logic Gates Implementation
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    Week 4: Verilog, K-Maps (with don't cares), and Implementation Technologies Week 4: Verilog, K-Maps (with don't cares), and Implementation Technologies
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    Week 5a: Implementation Technologies Week 5a: Implementation Technologies
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  • Assignment
    Lab 0: Getting Started with your FPGA Lab 0: Getting Started with your FPGA
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    Lab 1: The 2-bit Computer Lab 1: The 2-bit Computer
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  • Assignment
    Lab Assignment 1: A 2-bit CPU Design with Verilog and FPGAs Lab Assignment 1: A 2-bit CPU Design with Verilog and FPGAs
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  • Attachment
    Designing 4-to-1 MUX using always blocks, good designs versus correct-but-not-elegant ones: mymux.v Designing 4-to-1 MUX using always blocks, good designs versus correct-but-not-elegant ones: mymux.v
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Module 2: Number Representation & Arithmetic Circuits (Ch 3)

Module 2: Number Representation & Arithmetic Circuits (Ch 3)
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Module 2: Number Representation & Arithmetic Circuits (Ch 3) 4205955  
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    Module 2: Overview Module 2: Overview
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  • Page
    Week 5b: Addition, Signed Numbers, Ripple-Carry Adder Week 5b: Addition, Signed Numbers, Ripple-Carry Adder
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  • Assignment
    Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits
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    Week 6A: Subtraction, Overflow, Verilog Week 6A: Subtraction, Overflow, Verilog
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Module 3: Combinational Logic Circuits (Ch 4)

Module 3: Combinational Logic Circuits (Ch 4)
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Module 3: Combinational Logic Circuits (Ch 4) 4205956  
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    Module 3: Overview Module 3: Overview
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  • Page
    Week 6B: Multiplexor Design Week 6B: Multiplexor Design
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  • Page
    Week 7A: Multiplexors, decoders, encoders Week 7A: Multiplexors, decoders, encoders
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  • Assignment
    Lab Assignment 3: Verilog design of unsigned and 2's complement comparators Lab Assignment 3: Verilog design of unsigned and 2's complement comparators
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Module 4: Memory, Flip-Flop, Register, Counters (Ch 5)

Module 4: Memory, Flip-Flop, Register, Counters (Ch 5)
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Module 4: Memory, Flip-Flop, Register, Counters (Ch 5) 4205957  
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    Module 4: Overview Module 4: Overview
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  • Page
    Week 7B: Intro to SR Latch Week 7B: Intro to SR Latch
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Midterm and Final Exam information will be provided here

Midterm and Final Exam information will be provided here
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Midterm and Final Exam information will be provided here 4205970  
  • Context Module Sub Header

    The Midterm will be held in class on Feb. 26. Closed book. Closed Notes. Open Minds!

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  • Context Module Sub Header

    Mid-Term I Syllabus

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  • Context Module Sub Header

    Syllabus: i) Chapters 1 & 2: all sections; ii) Appexndix B: Section B.3 (static CMOS gates) and LUTs; iii) Chapter 3: all sections, EXCEPT Sec 3.7; iv) Chapter 4

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  • Attachment
    A Practice Test for you all: prac_midterm1.pdf A Practice Test for you all: prac_midterm1.pdf
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    Practice Midterm Review Practice Midterm Review
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  • Attachment
    Midterm1-cheatsheet.pdf Midterm1-cheatsheet.pdf
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HW Solutions

HW Solutions
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HW Solutions 4320068  
  • Attachment
    HW_1_Soln.pdf HW_1_Soln.pdf
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  • Attachment
    HW_2_Solution_Updated.pdf HW_2_Solution_Updated.pdf
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  • Attachment
    HW3_Solution (1).pdf HW3_Solution (1).pdf
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  • Attachment
    Homework 4 Solutions.pdf Homework 4 Solutions.pdf
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minimum score must view must submit must contribute