Course Modules

General References/Resources

General References/Resources
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General References/Resources 4205951  
  • Attachment
    Verilog Crash Course Verilog Crash Course
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    Online Resources Online Resources
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Module 0: Introduction

Module 0: Introduction
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Module 0: Introduction 4205953  
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    Module 0: Overview Module 0: Overview
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Module 1: Introduction To Digital Systems (Ch. 2 + App B)

Module 1: Introduction To Digital Systems (Ch. 2 + App B)
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Module 1: Introduction To Digital Systems (Ch. 2 + App B) 4205954  
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    Module 1: Overview Module 1: Overview
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    Week 1: Digital Circuit Design Application, Digital Abstraction, Boolean Functions Week 1: Digital Circuit Design Application, Digital Abstraction, Boolean Functions
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    Week 2: Boolean Functions, Universal Logic, Circuit Synthesis, K-Maps Week 2: Boolean Functions, Universal Logic, Circuit Synthesis, K-Maps
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    Week 3: Universal Logic, Karnaugh Map, Binary Decision Diagram, Logic Gates Implementation Week 3: Universal Logic, Karnaugh Map, Binary Decision Diagram, Logic Gates Implementation
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    Week 4: Verilog, K-Maps (with don't cares), and Implementation Technologies Week 4: Verilog, K-Maps (with don't cares), and Implementation Technologies
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    Week 5a: Implementation Technologies Week 5a: Implementation Technologies
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  • Assignment
    Lab 0: Getting Started with your FPGA Lab 0: Getting Started with your FPGA
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    Lab 1: The 2-bit Computer Lab 1: The 2-bit Computer
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  • Assignment
    Lab Assignment 1: A 2-bit CPU Design with Verilog and FPGAs Lab Assignment 1: A 2-bit CPU Design with Verilog and FPGAs
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  • Attachment
    Designing 4-to-1 MUX using always blocks, good designs versus correct-but-not-elegant ones: mymux.v Designing 4-to-1 MUX using always blocks, good designs versus correct-but-not-elegant ones: mymux.v
    Score at least   Must score at least   to complete this module item Scored at least   Module item has been completed by scoring at least   Score at least  % Must score at least  % to complete this module item Scored at least  % Module item has been completed by scoring at least  % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete

Module 2: Number Representation & Arithmetic Circuits (Ch 3)

Module 2: Number Representation & Arithmetic Circuits (Ch 3)
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Module 2: Number Representation & Arithmetic Circuits (Ch 3) 4205955  
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    Module 2: Overview Module 2: Overview
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  • Page
    Week 5b: Addition, Signed Numbers, Ripple-Carry Adder Week 5b: Addition, Signed Numbers, Ripple-Carry Adder
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  • Assignment
    Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits
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Module 3: Combinational Logic Circuits (Ch 4)

Module 3: Combinational Logic Circuits (Ch 4)
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Module 3: Combinational Logic Circuits (Ch 4) 4205956  
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    Module 3: Overview Module 3: Overview
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    Week 5: Multiplexor Design Week 5: Multiplexor Design
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minimum score must view must submit must contribute