Course Modules

General References/Resources

General References/Resources General References/Resources

Attachment

Verilog Crash Course Verilog Crash Course 1

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Page

Online Resources Online Resources 2

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Attachment

Midterm1-cheatsheet.pdf Midterm1-cheatsheet.pdf 3

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Discussion Sections

Discussion Sections Discussion Sections

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Discussion Section 1 (Week 6): CMOS, Overflow, Signed Multiplication Discussion Section 1 (Week 6): CMOS, Overflow, Signed Multiplication 1

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Discussion Section 2 (Week 7): Adder Design, Decoders, Comparator Design Discussion Section 2 (Week 7): Adder Design, Decoders, Comparator Design 2

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Discussion Section 3 (Week 10): Midterm Question + DFF Timing Issues Discussion Section 3 (Week 10): Midterm Question + DFF Timing Issues 3

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Discussion Section 4 (Week 11): FSM Design and Analysis Discussion Section 4 (Week 11): FSM Design and Analysis 4

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Page

Discussion Section 5 (Week 12): ASM + Functional Decomposition Discussion Section 5 (Week 12): ASM + Functional Decomposition 5

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Module 0: Introduction

Module 0: Introduction Module 0: Introduction

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Module 0: Overview Module 0: Overview 2

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Module 1: Introduction To Digital Systems (Ch. 2 + App B)

Module 1: Introduction To Digital Systems (Ch. 2 + App B) Module 1: Introduction To Digital Systems (Ch. 2 + App B)

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Module 1: Overview Module 1: Overview 1

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Page

Week 1: Digital Circuit Design Application, Digital Abstraction, Boolean Functions Week 1: Digital Circuit Design Application, Digital Abstraction, Boolean Functions 2

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Page

Week 2: Universal Logic, Circuit Synthesis, K-Maps Week 2: Universal Logic, Circuit Synthesis, K-Maps 3

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Page

Week 3: Karnaugh Map, Binary Decision Diagram, Logic Gates Implementation Week 3: Karnaugh Map, Binary Decision Diagram, Logic Gates Implementation 4

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Page

Lab 1: The 2-bit Computer Lab 1: The 2-bit Computer 5

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Attachment

Designing 4-to-1 MUX using always blocks, good designs versus correct-but-not-elegant ones: mymux.v Designing 4-to-1 MUX using always blocks, good designs versus correct-but-not-elegant ones: mymux.v 6

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Module 2: Number Representation & Arithmetic Circuits (Ch 3)

Module 2: Number Representation & Arithmetic Circuits (Ch 3) Module 2: Number Representation & Arithmetic Circuits (Ch 3)

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Module 2: Overview Module 2: Overview 1

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Page

Week 4: Addition, Signed Numbers, Ripple-Carry Adder Week 4: Addition, Signed Numbers, Ripple-Carry Adder 4

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Assignment

Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits 100 6

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Module 3: Combinational Logic Circuits (Ch 4)

Module 3: Combinational Logic Circuits (Ch 4) Module 3: Combinational Logic Circuits (Ch 4)

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Module 3: Overview Module 3: Overview 1

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Page

Week 5: Multiplexor Design Week 5: Multiplexor Design 3

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Week 6: Multiplexors, decoders, encoders Week 6: Multiplexors, decoders, encoders 5

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Assignment

Lab Assignment 3: Verilog design of unsigned and 2's complement comparators Lab Assignment 3: Verilog design of unsigned and 2's complement comparators 50 6

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Module 4: Memory, Flip-Flop, Register, Counters (Ch 5)

Module 4: Memory, Flip-Flop, Register, Counters (Ch 5) Module 4: Memory, Flip-Flop, Register, Counters (Ch 5)

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Module 4: Overview Module 4: Overview 1

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Week 7: Intro to SR Latch Week 7: Intro to SR Latch 3

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Week 8: SR Latch, DFF, Shift Register Week 8: SR Latch, DFF, Shift Register 4

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Week 9: Counters, Timing Issues Week 9: Counters, Timing Issues 5

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Assignment

Lab 4: Design of an electronic stopwatch Lab 4: Design of an electronic stopwatch 200 7

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Module 5: Synchronous Sequential Circuits

Module 5: Synchronous Sequential Circuits Module 5: Synchronous Sequential Circuits

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Module 5: Overview Module 5: Overview 1

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Week 10: Moore Machine, State-Assignment Problem Week 10: Moore Machine, State-Assignment Problem 2

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Week 11: Verilog + State Minimization Week 11: Verilog + State Minimization 3

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Week 12A: ASM + ASM Example Week 12A: ASM + ASM Example 4

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Assignment

Lab 5: Design of CPU Datapath + a control FSM + integration Lab 5: Design of CPU Datapath + a control FSM + integration 200 7

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Module 6: Optimized Design of Logic Circuits

Module 6: Optimized Design of Logic Circuits Module 6: Optimized Design of Logic Circuits

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Module 6: Overview Module 6: Overview 1

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Page

Week 12B: Functional Decomposition, Circuit Analysis Week 12B: Functional Decomposition, Circuit Analysis 2

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Week 13: Optimization Methods Week 13: Optimization Methods 3

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Labs

Labs Labs

Attachment

bcd_to_seven_seg_de10_lite.v bcd_to_seven_seg_de10_lite.v 6

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Assignment

Lab Assignment 1: A 2-bit CPU Design with Verilog and FPGAs Lab Assignment 1: A 2-bit CPU Design with Verilog and FPGAs 100 7

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Assignment

Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits Lab Assignment 2: Design, simulation, synthesis and implementation of adder circuits 100 8

assignment 27626763 1

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2024 HW Solutions

2024 HW Solutions 2024 HW Solutions

Attachment

HW3_Solution.pdf HW3_Solution.pdf 1

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Attachment

HW5_Solution.pdf HW5_Solution.pdf 2

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Midterm and Final Exam information will be provided here

Midterm and Final Exam information will be provided here Midterm and Final Exam information will be provided here

Context Module Sub Header

The Midterm will be held in class on Feb. 27. Closed book. Closed Notes. Open Minds! 1

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Context Module Sub Header

Mid-Term I Syllabus 2

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Context Module Sub Header

Syllabus: i) Chapters 1 & 2: all sections; ii) Appexndix B: Section B.3 (static CMOS gates) and Sec B.6 (PLDs); iii) Chapter 3: all sections, EXCEPT Sec 3.7; iv) Chapter 4 3

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Attachment

A Practice Test for you all: prac_midterm1.pdf A Practice Test for you all: prac_midterm1.pdf 4

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Page

Practice Midterm Review Practice Midterm Review 6

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
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Midterm Midterm 14

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
Attachment

Midterm Solutions Midterm Solutions 15

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
Context Module Sub Header

FINAL EXAM INFO 16

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
Context Module Sub Header

The final exam will be on Friday, April 25th, from 1:00 PM-3:00 PM in our classroom. You can find the list of topics in the page below. 17

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
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Final Exam Syllabus Final Exam Syllabus 18

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
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samplefinal.pdf samplefinal.pdf 19

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
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Practice Final Review (4/22/25) Practice Final Review (4/22/25) 20

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete
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FinalSolutions.pdf FinalSolutions.pdf 22

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Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete

Score at least Must score at least to complete this module item Scored at least Module item has been completed by scoring at least Score at least % Must score at least % to complete this module item Scored at least % Module item has been completed by scoring at least % View Must view in order to complete this module item Viewed Module item has been viewed and is complete Mark done Must mark this module item done in order to complete Marked done Module item marked as done and is complete Contribute Must contribute to this module item to complete it Contributed Contributed to this module item and is complete Submit Must submit this module item to complete it Submitted Module item submitted and is complete