Lab #1: Design with Verilog and FPGAs
- Due Feb 4, 2019 by 5pm
- Points 100
- Submitting a text entry box or a file upload
DE10_Lite_lab_Manual.pdf Download DE10_Lite_lab_Manual.pdf
DE10-Lite_User_Manual.pdf Download DE10-Lite_User_Manual.pdf
My_First_Fpga.pdf Download My_First_Fpga.pdf (This tutorial is for a slightly different board, but it still has some useful information in it.)
hdl_coding_style_altera.pdf Download hdl_coding_style_altera.pdf (Recommendations on Verilog coding style that may be useful.)
Rubric
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Keep in mind that 80 students have already been assessed using this rubric. Changing it will affect their evaluations.
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Working Demo
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Report
Brief written report that documents what you learned in this lab and optimizations that were done (if any).
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Schematic
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Verilog Code
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Verilog Testbenches
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Simulation results (annotated testbench waveforms).
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Total Points:
100
out of 100
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